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<title>PowerPC 600</title>

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PowerPC 600

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The PowerPC 600 family was the first family of <a href="PowerPC" title="PowerPC">PowerPC</a> <a href="Microprocessor" title="Microprocessor">processors</a> built. They were designed at the Somerset facility in <a href="Austin%2C_Texas" title="Austin, Texas">Austin, Texas</a>, jointly funded and staffed by engineers from <a href="IBM" title="IBM">IBM</a> and <a href="Motorola" title="Motorola">Motorola</a> as a part of the <a href="AIM_alliance" title="AIM alliance">AIM alliance</a>. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for <a href="Personal_computer" title="Personal computer">personal computers</a>. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

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</style><table class="sidebar nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="PowerPC" title="PowerPC">PowerPC</a>, and <a href="Power_ISA" title="Power ISA">Power ISA</a> architectures</th></tr><tr><th class="sidebar-heading" style="background:#DEDEDE">

NXP (formerly Freescale and Motorola)</th></tr><tr><td class="sidebar-content">

<ul><li>PowerPC e series (2006)

<ul><li>Qor series (2008)

<ul><li><a href="QorIQ" title="QorIQ">QorIQ</a></li>

<li><a href="Qorivva" title="Qorivva">Qorivva</a></li></ul></li></ul></td>

</tr><tr><th class="sidebar-heading" style="background:#DEDEDE">

IBM</th></tr><tr><td class="sidebar-content">

<ul><li><a href="IBM_Power_microprocessors" title="IBM Power microprocessors">Power</a> series (1990)

<ul><li><a href="POWER1" title="POWER1">POWER1</a></li>

<li><a href="POWER2" title="POWER2">POWER2</a></li>

<li><a href="POWER3" title="POWER3">POWER3</a></li>

<li><a href="POWER4" title="POWER4">POWER4</a></li>

<li><a href="POWER5" title="POWER5">POWER5</a></li>

<li><a href="POWER6" title="POWER6">POWER6</a></li>

<li><a href="POWER7" title="POWER7">POWER7</a></li>

<li><a href="POWER8" title="POWER8">POWER8</a></li>

<li><a href="POWER9" title="POWER9">POWER9</a></li>

<li><a href="Power10" title="Power10">Power10</a></li></ul></li></ul>

<ul><li>PowerPC series (1992)

<li><a href="IBM_A2" title="IBM A2">A2</a> (2010)

<li>RAD series (1997)

<ul><li><a href="IBM_RS64" title="IBM RS64">RS64</a> series (1996)</li></ul></td>

</tr><tr><th class="sidebar-heading" style="background:#DEDEDE">

IBM/Nintendo</th></tr><tr><td class="sidebar-content">

<ul><li><a href="Gekko_(processor)" title="Gekko (processor)">Gekko</a></li>

<li><a href="Broadway_(processor)" title="Broadway (processor)">Broadway</a></li>

<li><a href="Espresso_(processor)" title="Espresso (processor)">Espresso</a></li></ul></td>

</tr><tr><th class="sidebar-heading" style="background:#DEDEDE">

Other</th></tr><tr><td class="sidebar-content">

<ul><li><a href="Titan_(processor)" title="Titan (processor)">Titan</a></li>

<li><a href="PWRficient" title="PWRficient">PWRficient</a></li>

<li><a href="Xenon_(processor)" title="Xenon (processor)">Xenon</a></li>

</tr><tr><th class="sidebar-heading" style="background:#DEDEDE">

Related links</th></tr><tr><td class="sidebar-content">

<ul><li><a href="OpenPOWER_Foundation" title="OpenPOWER Foundation">OpenPOWER Foundation</a></li>

<li><a href="AIM_alliance" title="AIM alliance">AIM alliance</a></li>

<li><a href="Power.org" title="Power.org">Power.org</a></li>

<li><a href="AltiVec" title="AltiVec">AltiVec</a></li></ul></td>

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<div class="mw-heading mw-heading2"><h2 id="Nuclear_family">Nuclear family</h2></div>

<th>CPU

</th>

<th>Pipeline stages

</th>

<th>Features

</th></tr>

<tr>

<td>PowerPC 601

</td>

<td>4

</td>

<td>3 execution units, static branch prediction. SMP support.

</td></tr>

<tr>

<td>PowerPC 603

</td>

<td>4

</td>

<td>5 execution units, branch prediction. No SMP.

</td></tr>

<tr>

<td>PowerPC 604

</td>

<td>6

</td>

<td>Superscalar, out-of-order execution, 6 execution units. SMP support.

</td></tr>

<tr>

<td>PowerPC 620

</td>

<td>5

</td>

<td>Out-of-order execution- SMP support.

</td></tr></tbody></table>

<div class="mw-heading mw-heading3"><h3 id="PowerPC_601">PowerPC 601</h3></div>

The PowerPC 601 was the first generation of microprocessors to support the basic <a href="32-bit" class="mw-redirect" title="32-bit">32-bit</a> <a href="PowerPC" title="PowerPC">PowerPC</a> <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a>. The design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992. The first 601 processors were introduced in an IBM <a href="RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> <a href="Workstation" title="Workstation">workstation</a> in October 1993 (alongside its more powerful multichip cousin <a href="IBM" title="IBM">IBM</a> <a href="POWER2" title="POWER2">POWER2</a> line of processors) and the first Apple <a href="Power_Macintosh" title="Power Macintosh">Power Macintoshes</a> on March 14, 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an extremely aggressive schedule while including substantially new functionality (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBM <a href="RISC_Single_Chip" title="RISC Single Chip">RISC Single Chip</a> (RSC) processor,<a href="#cite_note-1">[1]</a> but also included support for the vast majority of the new PowerPC instructions not in the <a href="IBM_POWER_Instruction_Set_Architecture" class="mw-redirect" title="IBM POWER Instruction Set Architecture">POWER instruction set</a>. While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unified <a href="I/O" class="mw-redirect" title="I/O">I/O</a> <a href="Bus_(computing)" title="Bus (computing)">bus</a> structure and SMP/<a href="Memory_coherency" class="mw-redirect" title="Memory coherency">memory coherency</a> support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning. Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM and software developers in their transitions to PowerPC. From start of design to <a href="Tape-out" title="Tape-out">tape-out</a> of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.

In order to help the effort to rapidly incorporate the <a href="88110" class="mw-redirect" title="88110">88110</a> bus architecture to the 601 for the benefit of the alliance and its customers, Motorola management provided not only the 88110 bus architecture specifications, but also a handful of 88110 bus-literate designers to help with the 60x bus logic implementation and verification. Given the Apple system design team was familiar with the I/O bus structure from Motorola's 88110 and this I/O bus implementation was well defined and documented, the 601 team adopted the bus technology to improve time to market. The bus was renamed the 60x bus once implemented on the 601.<a href="#cite_note-2">[2]</a> These Motorola (and a small number of Apple) designers joined over 120 IBM designers in creating the 601.

Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their support <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASICs</a> and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses hadn't been adopted).

Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.

This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604, <a href="PowerPC_7xx" title="PowerPC 7xx">G3</a>, <a href="PowerPC_G4" title="PowerPC G4">G4</a> and Motorola/Freescale <a href="PowerQUICC" title="PowerQUICC">PowerQUICC</a> processors.

<div class="mw-heading mw-heading4"><h4 id="Design">Design</h4></div>

The chip was designed to suit a wide variety of applications and had support for external <a href="CPU_cache" title="CPU cache">L2 cache</a> and <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a>. It had four functional units, including a <a href="Floating-point_unit" title="Floating-point unit">floating-point unit</a>, an <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">integer unit</a>, a branch unit and a sequencer unit. The processor also included a <a href="Memory_management_unit" title="Memory management unit">memory management unit</a>. The integer <a href="Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipeline</a> was four stages long, the branch pipeline two stages long, the memory pipeline five stages long, and the floating-point pipeline six stages long.

First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and by Motorola as the MPC601. It operated at speeds ranging from 50 to 80 MHz. It was fabricated using a 0.6 μm <a href="CMOS" title="CMOS">CMOS</a> process with four levels of <a href="Aluminum_interconnect" class="mw-redirect" title="Aluminum interconnect">aluminum interconnect</a>. The die was 121 mm2 large and contained 2.8 million transistors. The 601 has a 32 KB unified <a href="CPU_cache" title="CPU cache">L1 cache</a>, a capacity that was considered large at the time for an on-chip cache. Thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competing <a href="Intel" title="Intel">Intel</a> <a href="P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">Pentium</a>. The PowerPC 601 was used in the first <a href="Power_Macintosh" title="Power Macintosh">Power Macintosh</a> computers from <a href="Apple_Inc." title="Apple Inc.">Apple</a>, and in a variety of <a href="RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> workstations and SMP servers from IBM and <a href="Groupe_Bull" title="Groupe Bull">Groupe Bull</a>.

IBM was the sole manufacturer of the 601 and 601+ microprocessors in its <a href="Burlington%2C_Vermont" title="Burlington, Vermont">Burlington, Vermont</a> and <a href="East_Fishkill%2C_New_York" title="East Fishkill, New York">East Fishkill, New York</a> production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola. These facts are somewhat obscured given there are various pictures of the "Motorola MPC601", particularly one specific case of masterful Motorola marketing where the 601 was named one of <a href="Time_(magazine)" title="Time (magazine)">Time Magazine</a>'s 1994 "Products of the Year" with a Motorola marking.

<ul><li><a rel="nofollow" class="external text" href="https://m.youtube.com/watch?v=BRoS_m1g1_Q">PowerPC 601 Microprocessor, lecture by Keith Diefendorff</a></li></ul>

<div class="mw-heading mw-heading4"><h4 id="PowerPC_601v">PowerPC 601v</h4></div>

An updated version, the PowerPC 601v or PowerPC 601+, operating at 90 to 120 MHz was introduced in 1994. It was fabricated in a newer 0.5 μm CMOS process with four levels of interconnect, resulting in a die measuring 74 mm2. The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBM <a href="Electronic_design_automation" title="Electronic design automation">EDA tools</a> on IBM systems and were fabricated in IBM-only facilities.<a href="#cite_note-3">[3]</a><a href="#cite_note-4">[4]</a><a href="#cite_note-5">[5]</a><a href="#cite_note-6">[6]</a>

<div class="mw-heading mw-heading3"><h3 id="PowerPC_603">PowerPC 603</h3></div>

The PowerPC 603 was the first processor implementing the complete 32-bit <a href="PowerPC" title="PowerPC">PowerPC Architecture</a> as specified. Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2 W and a small die of 85 mm2.<a href="#cite_note-7">[7]</a><a href="#cite_note-8">[8]</a><a href="#cite_note-9">[9]</a><a href="#cite_note-603_gerosa-10">[10]</a> It was designed to be a low cost, low power processor for portable applications. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating-point unit, <a href="Branch_predictor" title="Branch predictor">branch prediction unit</a>, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120 MHz at 3.8 V.<a href="#cite_note-603_gerosa-10">[10]</a> The 603 core did not have hardware support for <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a>.

The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm2 large drawing 2.2 W at 80 MHz.<a href="#cite_note-603_gerosa-10">[10]</a><a href="#cite_note-11">[11]</a> The 603 architecture is the direct ancestor to the <a href="PowerPC_7xx" title="PowerPC 7xx">PowerPC 750</a> architecture, marketed by Apple as the PowerPC "G3".

The 603 was intended to be used for portable <a href="List_of_Macintosh_models_grouped_by_CPU" class="mw-redirect" title="List of Macintosh models grouped by CPU">Apple Macintosh computers</a> but could not run <a href="Mac_68k_emulator" title="Mac 68k emulator">68K emulation software</a> with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line.<a href="#cite_note-12">[12]</a><a href="#cite_note-13">[13]</a> This caused the delay of the Apple <a href="PowerBook_5300" title="PowerBook 5300">PowerBook 5300</a> and <a href="PowerBook_Duo" title="PowerBook Duo">PowerBook Duo 2300</a>, as Apple chose to wait for a processor revision. Apple's use of the 603 in the <a href="Performa_5200" class="mw-redirect" title="Performa 5200">Performa 5200</a> line led to the processor getting a poor reputation. Aside from the issue of 68K emulation performance, the Performa machines shipped with a variety of design flaws, some of them severe, related to other aspects of the computers' design, including networking performance and stability, bus problems (width, speed, contention, and complexity), ROM bugs, and hard disk performance.<a href="#cite_note-14">[14]</a><a href="#cite_note-15">[15]</a> None of the problems of the 5200 line, aside from 68K emulation performance, were inherently due to the 603. Rather, the processor was retrofitted to be used with 68K motherboards and other obsolete parts.<a href="#cite_note-16">[16]</a> The site Low End Mac rates the Performa 5200 as the worst Mac of all-time.<a href="#cite_note-17">[17]</a> The 603 found widespread use in different embedded appliances.

<div class="mw-heading mw-heading4"><h4 id="PowerPC_603e_and_603ev">PowerPC 603e and 603ev</h4></div>

The performance issues of the 603 were addressed in the PowerPC 603e. The L1 cache was enlarged and enhanced to 16 KB four-way set-associative data and instruction caches. The clock speed of the processors was doubled too, reaching 200 MHz. Shrinking the fabrication process to 350 nm allowed for speeds of up to 300 MHz. This part is sometimes called PowerPC 603ev. The 603e and 603ev have 2.6 million transistors each and are 98 mm2 and 78 mm2 large respectively. The 603ev draws a maximum of 6 W at 300 MHz.<a href="#cite_note-18">[18]</a><a href="#cite_note-19">[19]</a>

The PowerPC 603e was the first mainstream desktop processor to reach 300 MHz, as used in the <a href="Power_Macintosh_6500" title="Power Macintosh 6500">Power Macintosh 6500</a>. The 603e was also used in accelerator cards from <a href="Phase5" title="Phase5">Phase5</a> for the <a href="Amiga" title="Amiga">Amiga</a> line of computers, with CPUs ranging in speeds from 160 to 240 MHz. The PowerPC 603e is still sold today by IBM and Freescale, and others like <a href="Atmel" title="Atmel">Atmel</a> and <a href="Honeywell" title="Honeywell">Honeywell</a> who makes the <a href="Radiation_hardened" class="mw-redirect" title="Radiation hardened">radiation hardened</a> variant <a href="RHPPC" title="RHPPC">RHPPC</a>. The PowerPC 603e was also the heart of the <a href="BeBox" title="BeBox">BeBox</a> from <a href="Be_Inc." title="Be Inc.">Be Inc.</a> The BeBox is notable since it is a <a href="Multiprocessing" title="Multiprocessing">multiprocessing</a> system, something the 603 wasn't designed for. IBM also used PowerPC 603e processors in the <a href="IBM_ThinkPad_800_series" class="mw-redirect" title="IBM ThinkPad 800 series">IBM ThinkPad 800 series</a>. In certain digital oscilloscope series, <a href="LeCroy_Corporation" title="LeCroy Corporation">LeCroy</a> used the PowerPC 603e as the main processor.<a href="#cite_note-20">[20]</a><a href="#cite_note-21">[21]</a> The 603e processors also power all 66 <a href="Iridium_(satellite)" class="mw-redirect" title="Iridium (satellite)">satellites</a> in the <a href="Iridium_Satellite_LLC" class="mw-redirect" title="Iridium Satellite LLC">Iridium</a> satellite phone fleet. The satellites each contain seven Motorola/Freescale PowerPC 603e processors running at roughly 200 MHz each. A custom 603e processor is also used in the <a href="Mark_54_Lightweight_Torpedo" class="mw-redirect" title="Mark 54 Lightweight Torpedo">Mark 54 Lightweight Torpedo</a>.

The PowerPC 603e core, renamed G2 by <a href="Freescale" class="mw-redirect" title="Freescale">Freescale</a>, is the basis for many embedded <a href="PowerQUICC#PowerQUICC_II" title="PowerQUICC">PowerQUICC II</a> processors, and, as such, it keeps on being developed. Freescale's PowerQUICC II <a href="System-on-a-chip" class="mw-redirect" title="System-on-a-chip">SoC</a> processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz. The G2 name is also used as a retronym for the 603e and 604 processors to align with the G3, G4, and the G5.

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</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="PowerPC_e300" title="PowerPC e300">PowerPC e300</a></div>

Freescale has enhanced the 603e core, calling it e300, in the <a href="PowerQUICC#PowerQUICC_II_Pro" title="PowerQUICC">PowerQUICC II Pro</a> embedded processors. Larger 32/32 KB L1 caches and other performance enhancing measures were added. Freescale's PowerQUICC II Pro <a href="System-on-a-chip" class="mw-redirect" title="System-on-a-chip">SoC</a> processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz. The e300 is also the core of the <a href="PowerPC_5000#MPC52xx" title="PowerPC 5000">MPC5200B</a> SoC processor that is used in the small <a href="EFIKA" class="mw-redirect" title="EFIKA">EFIKA</a> computer.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_604">PowerPC 604</h3></div>

The PowerPC 604 was introduced in December 1994 alongside the 603 and was designed as a high-performance chip for <a href="Workstation" title="Workstation">workstations</a> and entry-level servers and as such had support for <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> in hardware. The 604 was used extensively in <a href="Apple_Inc." title="Apple Inc.">Apple</a>'s high-end systems and was also used in <a href="Macintosh_clone" title="Macintosh clone">Macintosh clones</a>, IBM's low-end <a href="RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> servers and workstations, <a href="Amiga" title="Amiga">Amiga</a> accelerator boards, and as an embedded CPU for telecom applications.

The 604 is a <a href="Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> processor capable of issuing four instructions simultaneously. The 604 has a six-stage pipeline and six execution units that can work in parallel, finishing up to six instructions every cycle. It has two simple and one complex <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">integer units</a>, one <a href="Floating-point_unit" title="Floating-point unit">floating-point unit</a>, one branch-processing unit managing <a href="Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a>, and one load/store unit. It has separate 16 KB data and instruction L1 caches. The external interface is a 32- or 64-bit 60x bus that operates at clock rates up to 50 MHz.

The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5 μm CMOS process with four levels of interconnect. The die measured 12.4 mm by 15.8 mm (196 mm2) and drew 14-17 W at 133 MHz. It operated at speeds between 100 and 180 MHz.<a href="#cite_note-22">[22]</a><a href="#cite_note-23">[23]</a><a href="#cite_note-24">[24]</a>

<ul><li><a rel="nofollow" class="external text" href="https://m.youtube.com/watch?v=Vm0itpIc80g">Power PC 604 RISC microprocessor, lecture by Marvin Denman</a></li></ul>

<div class="mw-heading mw-heading4"><h4 id="PowerPC_604e">PowerPC 604e</h4></div>

The PowerPC 604e was introduced in July 1996 and added a condition register unit and separate 32 KB data and instruction L1 caches among other changes to its memory subsystem and branch prediction unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35 μm CMOS process with five levels of interconnect. The die was 148 mm2 or 96 mm2 large, manufactured by Motorola and IBM respectively, drawing 16–18 W at 233 MHz. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.<a href="#cite_note-25">[25]</a><a href="#cite_note-26">[26]</a>

<div class="mw-heading mw-heading4"><h4 id="PowerPC_604ev_"Mach5"">PowerPC 604ev "Mach5"</h4></div>

The PowerPC 604ev, 604r or "Mach 5" was introduced in August 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption. The die was 47 mm2 small manufactured on a 0.25 μm CMOS process with five levels of interconnect, and drew 6 W at 250 MHz. It operated at speeds between 250 and 400 MHz and supported a memory bus up to 100 MHz.

While Apple dropped the 604ev in 1998 in favor for the <a href="PowerPC_750" class="mw-redirect" title="PowerPC 750">PowerPC 750</a>, IBM kept using it in entry-level models of its <a href="RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> computers for several years.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_620">PowerPC 620</h3></div>

The PowerPC 620 was the first implementation of the entire <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a> PowerPC architecture. It was a second generation PowerPC alongside the 603 and 604, but geared towards the high-end workstation and server market. It was powerful on paper and was initially supposed to be launched alongside its brethren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e surpassed it.<a href="#cite_note-27">[27]</a> The 620 was therefore never produced in large quantities and found very little use. The sole user of PowerPC 620 was <a href="Groupe_Bull" title="Groupe Bull">Groupe Bull</a> in its Escala <a href="UNIX" class="mw-redirect" title="UNIX">UNIX</a> machines, but they didn't deliver any large numbers. IBM, which intended to use it in workstations and servers, decided to wait for the even more powerful <a href="RS64" class="mw-redirect" title="RS64">RS64</a> and <a href="POWER3" title="POWER3">POWER3</a> 64-bit processors instead.

The 620 was produced by Motorola in a 0.5 μm process. It had 6.9 million transistors and the die had an area of 311 mm2. It operated at clock rates between 120 and 150 MHz, and drew 30 W at 133 MHz. A later model was built using a 0.35 μm process, enabling it to reach 200 MHz.

The 620 was similar to the 604. It has a five-stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units. With larger 32 KB instruction and data caches, support for a L2 cache that may have a capacity of 128 <a href="Megabyte" title="Megabyte">MB</a>, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604. The floating-point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instructions in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.

<div class="mw-heading mw-heading4"><h4 id="6XX,_MX,_and_future_buses">6XX, MX, and future buses</h4></div>

The system bus was a wider and faster 128-bit memory bus called the 6XX bus. It was designed to be a system bus for multiprocessor systems where processors, caches, memory and I/O was to be connected, assisted by a system control chip. It supports both 32- and 64-bit PowerPC processors, memory addresses larger than 32 bits, and <a href="Non-Uniform_Memory_Access" class="mw-redirect" title="Non-Uniform Memory Access">NUMA</a> environments. It was also used in POWER3, RS64, as well as 604-based RS/6000 systems (with the "Orca" bridge chip<a href="#cite_note-28">[28]</a>).<a href="#cite_note-29">[29]</a>

The MX IO but was utilized for IO connection in 6xx based systems. The chipsets (initially named after snakes) featured bridges between the 6xx and MX bus, with additional chips to bridge between the MX and standard IO busses.

The 6XX bus later evolved into a distributed coherent bus refereed to as the Fabric Bus, while the MX bus evolved into the GX bus(The G in reference to the project codename GigaProcessor), both utilized in the <a href="POWER4" title="POWER4">POWER4</a>. Later GX+ and GX++ in <a href="POWER5" title="POWER5">POWER5</a> and <a href="POWER6" title="POWER6">POWER6</a> respectively. The GX bus is also used in IBM's <a href="IBM_System_z10" title="IBM System z10">z10</a> and <a href="IBM_zEnterprise_System" class="mw-redirect" title="IBM zEnterprise System">z196</a> <a href="IBM_System_z" class="mw-redirect" title="IBM System z">System z</a> mainframes.

<ul><li><a rel="nofollow" class="external text" href="http://www.feb-patrimoine.com/Histoire/temoignages/histoire_unix_chez_bull_12_2004.pdf">Contribution to the history of Unix at Bull</a> (Interesting reading concerning the use of PowerPC 620 at Bull. In French)</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Extended_family">Extended family</h2></div>

<div class="mw-heading mw-heading3"><h3 id="PowerPC_602">PowerPC 602</h3></div>

The PowerPC 602 was a stripped-down version of PowerPC 603, specially made for game consoles by Motorola and IBM, introduced in February 1995.<a href="#cite_note-NGen6-30">[30]</a> It has smaller L1 caches (4 KB instruction and 4 KB data), a single-precision floating-point unit<a href="#cite_note-NGen6-30">[30]</a> and a scaled back branch prediction unit. It was offered at speeds ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It consisted of 1 million transistors and it was 50 mm2 large manufactured in a 0.5 μm, CMOS process with four levels of interconnect.<a href="#cite_note-31">[31]</a>

<a href="The_3DO_Company" title="The 3DO Company">3DO</a> developed the <a href="Panasonic_M2" title="Panasonic M2">M2 game console</a> that used two PowerPC 602,<a href="#cite_note-NGen6-30">[30]</a><a href="#cite_note-32">[32]</a> but it was never marketed.

<ul><li><a rel="nofollow" class="external text" href="http://www.cpushack.com/CIC/embed/announce/IBMPowerPC602.html">Article at the CPUShack</a></li></ul>

<div class="mw-heading mw-heading3"><h3 id="PowerPC_603q">PowerPC 603q</h3></div>

On October 21, 1996, the <a href="Fabless_semiconductor_company" class="mw-redirect" title="Fabless semiconductor company">fabless semiconductor company</a> <a href="Quantum_Effect_Devices" title="Quantum Effect Devices">Quantum Effect Devices</a> (QED) announced a PowerPC 603-compatible processor named "PowerPC 603q" at the <a href="Microprocessor_Report" title="Microprocessor Report">Microprocessor Forum</a>. Despite its name, it did not have anything in common with any other 603. It was a from the ground up implementation of the 32-bit PowerPC architecture targeted at the high-end embedded market developed over two years. As such, it was small, simple, energy efficient, but powerful; equaling the more expensive 603e while drawing less power. It had an in-order, five-stage pipeline with a single integer unit, a <a href="Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision</a> floating-point unit (FPU) and separate 16 KB instruction and 8 KB data caches. While the integer unit was a brand new design, the FPU was derived from the <a href="R4600" title="R4600">R4600</a> to save time. It was 69 mm2 small using a 0.5 μm fabrication process and drew just 1.2 W at 120 MHz.<a href="#cite_note-33">[33]</a><a href="#cite_note-34">[34]</a>

The 603q was designed for Motorola, but they withdrew from the contract before the 603q went into full production. As a result, the 603q was canceled as QED could not continue to market the processor since they lacked a PowerPC license of their own.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_613">PowerPC 613</h3></div>

"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC.<a href="#cite_note-CPUShack-ppc95-35">[35]</a><a href="#cite_note-36">[36]</a><a href="#cite_note-MacKiDo-codenames-37">[37]</a> It supposedly was renamed "<a href="PowerPC_750" class="mw-redirect" title="PowerPC 750">PowerPC 750</a>" in response to <a href="Exponential_Technology" title="Exponential Technology">Exponential Technology</a>'s <a href="X704" title="X704">x704</a> processor that was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_614">PowerPC 614</h3></div>

Similar to PowerPC 613, the "PowerPC 614" might have been a name given by Motorola to a third generation PowerPC,<a href="#cite_note-CPUShack-ppc95-35">[35]</a><a href="#cite_note-MacKiDo-codenames-37">[37]</a> and later renamed by the same reason as 613. It's been suggested that the part was renamed "<a href="PowerPC_G4" title="PowerPC G4">PowerPC 7400</a>", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_615">PowerPC 615</h3></div>

The "PowerPC 615" is a PowerPC processor announced by IBM in 1994, but which never reached <a href="Mass_production" title="Mass production">mass production</a>. Its main feature was to incorporate an <a href="X86" title="X86">x86</a> core on die, thus making the processor able to natively process both PowerPC and x86 instructions.<a href="#cite_note-38">[38]</a> An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 were <a href="Minix" title="Minix">Minix</a> and a special development version of <a href="OS/2" title="OS/2">OS/2</a>.<a href="#cite_note-39">[39]</a>

It was 330 mm2 large and manufactured by IBM on a 0.35 μm process. It was pin compatible with <a href="Intel" title="Intel">Intel</a>'s <a href="Pentium" title="Pentium">Pentium</a> processors and comparable in speed. The processor was introduced only as a prototype and the program was killed in part by the fact that <a href="Microsoft" title="Microsoft">Microsoft</a> never supported the processor. Engineers working on the PowerPC 615 would later find their way to <a href="Transmeta" title="Transmeta">Transmeta</a>, where they worked on the <a href="Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a> processor. With progress having been demonstrated in the development of dynamic translation software, such as Digital's <a href="FX!32" title="FX!32">FX!32</a> technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.<a href="#cite_note-electronicnews19951106_digital-40">[40]</a>: <span title="Pages: 94

Quotation: "The performance levels the 615 is targeting, as we understand, are so degraded by the fact that you're giving up hardware to put that x86 emulation on-chip that it's just uncompelling."" class="tooltip tooltip-dashed" style="border-bottom: 1px dashed;">94

<div class="mw-heading mw-heading3"><h3 id="PowerPC_625">PowerPC 625</h3></div>

"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "<a href="RS64" class="mw-redirect" title="RS64">RS64</a>". The designation "PowerPC 625" was never used for the final processors.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_630">PowerPC 630</h3></div>

"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the <a href="IBM_POWER_Instruction_Set_Architecture" class="mw-redirect" title="IBM POWER Instruction Set Architecture">POWER</a> and <a href="PowerPC" title="PowerPC">PowerPC</a> instruction sets. It was later renamed "<a href="POWER3" title="POWER3">POWER3</a>", probably to distinguish it from the more consumer oriented "PowerPC" processors used by <a href="Apple_Inc." title="Apple Inc.">Apple</a>.

<div class="mw-heading mw-heading3"><h3 id="PowerPC_641">PowerPC 641</h3></div>

"PowerPC 641", codename Habanero, is a defunct PowerPC project by IBM in the 1994–96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor.<a href="#cite_note-41">[41]</a><a href="#cite_note-42">[42]</a>

<ul><li><a href="PowerPC_970" title="PowerPC 970">PowerPC 970</a></li>

<li><a href="IBM_POWER_architecture" title="IBM POWER architecture">IBM POWER architecture</a></li>

<li><a href="IBM_Power_microprocessors" title="IBM Power microprocessors">IBM Power microprocessors</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li>

<li><a href="List_of_Mac_models_grouped_by_CPU_type" title="List of Mac models grouped by CPU type">List of Mac models grouped by CPU type</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFStokes2004" class="citation web cs1">Stokes, Jon (August 3, 2004). <a rel="nofollow" class="external text" href="https://arstechnica.com/features/2004/08/ppc-1/2/">"PowerPC on Apple: An Architectural History, Part I (page 2, "PowerPC 601")"</a>. <a href="Ars_Technica" title="Ars Technica">Ars Technica</a>.</cite>

</li>

<li id="cite_note-2"><a href="#cite_ref-2">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF7785256996007248B1/$file/60xbus.pdf">"The Bus Interface for 32-Bit Microprocessors"</a> (PDF). <a href="Motorola" title="Motorola">Motorola</a>. 1997.</cite>

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<li id="cite_note-3"><a href="#cite_ref-3">^</a> <cite id="CITEREFAllenBecker1993" class="citation conference cs1">Allen, M.; Becker, M (February 1993). Multiprocessing Aspects of the PowerPC 601 Microprocessor. Compcon. pp. 117–126.</cite>

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<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<ul><li><cite id="CITEREFWeissSmith1994" class="citation book cs1">Weiss, Shlomo; Smith, James Edward (1994). POWER and PowerPC. Morgan Kaufmann. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>1558602798</bdi>.</cite> — Relevant parts: Chapter 8 (describes the PowerPC 601), and Chapter 11 (a comparison of the PowerPC 601 and Alpha 21064)</li></ul>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://www.mackido.com/Hardware/G2.html">PPC 600 at mackido.com</a></li></ul></div><div><div class="zim-footer">

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